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ma5114 1/12 the ma5114 4k static ram is configured as 1024 x 4 bits and manufactured using cmos-sos high performance, radiation hard, 3 m m technology. the design uses a 6 transistor cell and has full static operation with no clock or timing strobe required. address input buffers are deselected when chip select is in the high state. features n 3 m m cmos-sos technology n latch-up free n fast access time 90ns typical n total dose 10 6 rad(si) n transient upset >10 10 rad(si)/sec n seu <10 -10 errors/bitday n single 5v supply n three state output n low standby current 50 m a typical n -55 c to +125 c operation n all inputs and outputs fully ttl or cmos compatible n fully static operation n data retention at 2v supply figure 2: block diagram operation mode cs we i/o power read l h d out isb1 write l l d in standby h x high z isb2 figure 1: truth table ma5114 radiation hard 1024x4 bit static ram replaces june 1999 version, ds3591-4.0 ds3591-5.0 january 2000
ma5114 2/12 symbol parameter min. max. units v cc supply voltage -0.5 7 v v i input voltage -0.3 v dd +0.3 v t a operating temperature -55 125 c t s storage temperature -65 150 c figure 3: absolute maximum ratings stresses above those listed may cause permanent damage to the device. this is a stress rating only and functlonal operation of the device at these condltions, or at any other condition above those indicated in the operations section of this specification, is not implied exposure to absolute maxlmum rating conditions for extended perlods may affect device reliability. notes for tables 4 and 5: 1. characteristics apply to pre radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10% (characteristics at higher radiation levels available on request). 2. worst case at t a = +125 c, guaranteed but not tested at t a = -55 c. group a subgroups 1, 2, 3. symbol parameter conditions min. typ. max. units v dd supply voltage - 4.5 5.0 5.5 v v lh input high voltage - v dd /2 - v dd v v ll input low voltage - v ss - 0.8 v v oh output high voltage i oh1 = -1ma 2.4 - - v v ol output low voltage i ol = 2ma - - 0.4 v i li input leakage current (note 2) all inputs except cs -- 10 m a i lo output leakage current (note 2) output disabled, v out = v ss or v dd -- 20 m a i pui input pull-up current v in = v ss on cs input only - - -100 m a i pdi input leakage current v in = v ss on cs input only - - 5 m a i dd power supply current f rc = 1mhz, cs = 50% mark:space- 12 16 ma i sb1 selected supply current cs = v ss -2535ma i sb2 standby supply current chip disabled - 50 3000 m a figure 4: electrical characteristics symbol parameter conditions min. typ. max. units v dr v cc for data retention cs = v dr 2.0 - - v i ddr data retention current cs = v dr , v dr = 2.0v - 30 2000 m a figure 5: data retention characteristics characteristics and ratings
ma5114 3/12 ac characteristics conditions of test for tables 5 and 6: 1. input pulse = v ss to 3.0v. 2. times measurement reference level = 1.5v. 3. transition is measured at 500mv from steady state. 4. this parameter is sampled and not 100% tested. notes for tables 6 and 7: characteristics apply to pre-radiation at t a = -55 c to +125 c with v dd = 5v 10% and to post 100k rad(si) total dose radiation at t a = 25 c with v dd = 5v 10%. group a subgroups 9, 10, 11. symbol parameter min max units t avavr read cycle time 135 - ns t avqv address access time - 135 ns t elqv chip select to output valid - 135 ns t elqx (3,4) chip select to output active 10 - ns t elqz (3,4) chip select to output tri state 10 50 ns t axqx output hold from address change 10 - ns figure 6: read cycle ac electrical characteristics symbol parameter min max units t avavw write cycle tlme 135 - ns t avwl address set up time 10 - ns t wlwh write pulse width 50 - ns t whav write recovery time 5 - ns t dvwh data set up time 35 - ns t nhdx data hold time 5 - ns t wlqz (3,4) write enable to output tri state 10 50 ns t elwl chip selection to write low 25 - ns t elwh chip selection to end of write 85 - ns t avwh address valid to end of write 80 - ns t whqx (3,4) output active from end to write 5 - ns figure 7: write cycle ac electrical characteristics symbol parameter conditions min. typ. max. units c in input capacitance v l = 0v - 6 10 pf c out output capacitance v o = 0v - 8 12 pf note: t a = 25 c and f = 1mhz. data obtained by characterisation or analysis; not routinely measured. figure 8: capacitance
ma5114 4/12 symbol parameter conditions f t basic functionality v dd = 4.5v - 5.5v, freq = 1mhz v il = v ss , v ih = v dd , v ol 1.5v, v oh 3 1.5v temp = -55 c to +125 c, gps pattern set group a subgroups 7, 8a, 8b figure 9: functionality subgroup definition 1 static characteristics specified in tables 4 and 5 at +25 c 2 static characteristics specified in tables 4 and 5 at +125 c 3 static characteristics specified in tables 4 and 5 at -55 c 7 functional characteristics specified in table 9 at +25 c 8a functional characteristics specified in table 9 at +125 c 8b functional characteristics specified in table 9 at -55 c 9 switching characteristics specified in tables 6 and 7 at +25 c 10 switching characteristics specified in tables 6 and 7 at +125 c 11 switching characteristics specified in tables 6 and 7 at -55 c figure 10: definition of subgroups
ma5114 5/12 timing diagrams figure 11a: read cycle 1 1. we is high for read cycle. 2. address vaild prior to or coincident with cs transition low. t avavr t avqv t axqx t elqv t elqx t ehqz address cs data out high impedance data valid figure 11b: read cycle 2 1. we is high for read cycle. 2. device is continually selected. cs low. t avavr t avqv t axqx address data out data valid
ma5114 6/12 figure 12: write cycle address t avavw t avwh t avwl t wlwh (2) t whav (3) t elwl (7) (4) t wlqz we t axqx t wlqh data out (5) (6) high impedance data valid data in t dvwh t whdx t elwh cs 1. we must be high during all address transitions. 2. a write occurs during the overlap (t wlwh ) of a low cs and a low we . 3. t whav is measured from either cs or we going high, whichever is the earlier, to the end of the write cycle. 4. if the cs low transition occurs simultaneously with, or after, the we low transition, the output remains in the high impedance state. 5. data out is in the active state, so data in must not be in opposing state. 6. data out is the write data of the current cycle, if selected. 7. data out is the read data of the next address, if selected. 8. t elwl must be met to prevent memory corruption.
ma5114 7/12 outlines and pin assignments figure 13: 18-lead ceramic dil (solder seal) - package style c ref millimetres inches min. nom. max. min. nom. max. a - - 5.715 - - 0.225 a1 0.38 - 1.53 0.015 - 0.060 b 0.35 - 0.59 0.014 - 0.023 c 0.20 - 0.36 0.008 - 0.014 d - - 23.11 - - 0.910 e - 2.54 typ. - - 0.100 typ. - e1 - 8.13 typ. - - 0.300 typ. - h 4.44 - 5.38 0.175 - 0.212 me - - 8.28 - - 0.326 z - - 1.27 - - 0.050 w - - 1.53 - - 0.060 xg406 d w a e b z h a 1 15 m e c e 1 seating plane 1 9 18 10 18 vdd 17 a7 16 a8 15 a9 14 d1 13 d2 12 d3 11 d4 10 we 1 a6 2 a5 3 a4 4 a3 5 a0 6 a1 7 a2 8 cs 9 vss top view
ma5114 8/12 figure 14: 24-lead ceramic flatpack (solder seal) - package style f m b e d l a a1 c pin 1 z m e ref millimetres inches min. nom. max. min. nom. max. a - - 3.07 - - 0.121 a1 0.66 - - 0.026 - - b 0.38 - 0.48 0.015 - 0.019 c 0.08 - 0.152 0.003 - 0.006 d 14.99 - 15.50 0.590 - 0.610 e - 2.54 - - 0.050 - l 6.73 - 7.75 0.265 - 0.305 m 9.96 - 10.36 0.392 - 0.408 me 7.6 - - 0.30 - - z 0.13 - 1.14 0.005 - 0.045 xg544 1nc 2a6 3a5 4a4 5a3 6nc 7a0 8a1 9a2 10 nc 11 cs 12 vss 24 vdd 23 a7 22 a8 21 a9 20 nc 19 nc 18 d1 17 d2 16 d3 15 d4 14 nc 13 we bottom view
ma5114 9/12 figure 15: 24-pad leadless chip carrier - package style l bottom view pad 1 radius r 3 corners e e b 1 d a bottom view 3 2 1 24 23 22 10 11 12 13 14 15 n c cs vss we n c d4 a5 a6 n c vdd a7 a8 9 8 7 6 5 4 a4 a3 nc a0 a1 a2 16 17 18 19 20 21 a9 nc nc d1 d2 d3 ref millimetres inches min. nom. max. min. nom. max. a - - 2.16 - - 0.096 b1 - 0.51 - - 0.020 - d 8.76 - 9.14 0.345 - 0.360 e 8.76 - 9.14 0.345 - 0.360 e - 1.02 - - 0.040 - r - 0.19 - - 0.0075 - xg470
ma5114 10/12 package option burnin function f c l via static 1 static 2 dynamic radiation a6 2 1 2 r 0v 5v f6 5v a5 3 2 3 r 0v 5v f5 5v a4 4 3 4 r 0v 5v f4 5v a3 5 4 5 r 0v 5v f3 5v a0 7 5 7 r 0v 5v f0 5v a1 8 6 8 r 0v 5v f1 5v a2 9 7 9 r 0v 5v f2 5v ncs 11 8 11 r 0v 5v 0v 5v vss 12 9 12 direct 0v 0v 0v 0v nwe 13 10 13 r 0v 5v 5v 5v d4 15 11 15 r 0v 5v load 5v d3 16 12 16 r 0v 5v load 5v d2 17 13 17 r 0v 5v load 5v d1 18 14 18 r 0v 5v load 5v a9 21 15 21 r 0v 5v f9 5v a8 22 16 22 r 0v 5v f8 5v a7 23 17 23 r 0v 5v f7 5v vdd 24 18 24 direct 5v 5v 5v 5v 1. f0=150khz, f1=f0/2, f2=f0/4, f3=f0/8 etc. 2. burnin r=1k 3. radiation r=10k figure 16: burnin and radiation configuration
ma5114 11/12 radiation tolerance total dose radiation testing for product procured to guaranteed total dose radiation levels, each wafer lot will be approved when all sample devices from each lot pass the total dose radiation test. the sample devices will be subjected to the total dose radiation level (cobalt-60 source), defined by the ordering code, and must continue to meet the electrical parameters specified in the data sheet. electrical tests, pre and post irradiation, will be read and recorded. gec plessey semiconductors can provide radiation testing compliant with mil-std-883 test method 1019, ionizing radiation (total dose). ion let (mev.cm 2 /mg) upset bit cross-section (cm 2 /bit) figure 18: typical per-bit upset cross-section vs ion let single event upset characteristics total dose (function to specification)* 1x10 5 rad(si) transient upset (stored data loss) 5x10 10 rad(si)/sec transient upset (survivability) >1x10 12 rad(si)/sec neutron hardness (function to specification) >1x10 15 n/cm 2 single event upset** 3.4x10 -9 errors/bit day latch up not possible * other total dose radiation levels available on request ** worst case galactic cosmic ray upset - interplanetary/high altitude orbit figure 17: radiation hardness parameters
ma5114 12/12 ordering information for details of reliability, qa/qc, test and assembly options, see manufacturing capability and quality assurance standards section 9. unique circuit designator s l c r radiation hard processing 30 krads (si) guaranteed 50 krads (si) guaranteed 100 krads (si) guaranteed radiation tolerance c f l ceramic dil (solder seal) flatpack (solder seal) leadless chip carrier package type qa/qci process (see section 9 part 4) test process (see section 9 part 3) assembly process (see section 9 part 2) l c d e b s rel 0 rel 1 rel 2 rel 3/4/5/stack class b class s reliability level max5114xxxxx customer service centres france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 north america tel: 011-800-5554-5554. fax: 011-800-5444-5444 uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 sales offices france, benelux, italy and spain tel: +33 (0)1 69 18 90 00. fax: +33 (0)1 64 46 54 50 germany tel: 07351 827723 north america tel: (613) 723-7035. fax: (613) 723-1518. toll free: 1.888.33.dynex (39639) / tel: (831) 440-1988. fax: (831) 440-1989 / tel: (949) 733-3005. fax: (949) 733-2986. uk, germany, scandinavia & rest of world tel: +44 (0)1522 500500. fax: +44 (0)1522 500020 these offices are supported by representatives and distributors in many countries world-wide. ? dynex semiconductor 2000 publication no. ds3581-5 issue no. 5.0 january 2000 technical documentation C not for resale. printed in united kingdom headquarters operations dynex semiconductor ltd doddington road, lincoln. lincolnshire. ln6 3lf. united kingdom. tel: 00-44-(0)1522-500500 fax: 00-44-(0)1522-500550 dynex power inc. unit 7 - 58 antares drive, nepean, ontario, canada k2e 7w6. tel: 613.723.7035 fax: 613.723.1518 toll free: 1.888.33.dynex (39639) this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior notice the specification, design or price of any product or service. information con cerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to f ully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request. all brand names and product names used in this publication are trademarks, registered trademarks or trade names of their respec tive owners. http://www.dynexsemi.com e-mail: power_solutions@dynexsemi.com datasheet annotations: dynex semiconductor annotate datasheets in the top right hard corner of the front page, to indicate product status. the annota tions are as follows:- target information: this is the most tentative form of information and represents a very preliminary specification. no actual design work on the product has been started. preliminary information: the product is in design and development. the datasheet represents the product as it is understood but details may change. advance information: the product design is complete and final characterisation for volume production is well in hand. no annotation: the product parameters are fixed and the product is available to datasheet specification.

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